By Matthew Dublin
Researchers at Ohio Supercomputer Center (OSC) have announced that they will start developing code with Intel’s Many Integrated Core Architecture (Intel MIC) for scientific computing workloads. Over the next six months, OSC staff will evaluate the capabilities of the Intel MIC Architecture across a range of HPC application areas including computational chemistry, climate and ocean modeling, high-energy physics, and computational material sciences.
In order to help the OSC team kick the tires on this new chip architecture, Intel will provide the staff with early access to the first commercial Intel MIC coprocessor code-named “Knights Corner.” The new chip is a massively parallel x86 processor slated to debut with 50 cores. The technology behind “Knights Corner” is actually based in part on the canceled “Larrabee” project — Intel’s failed attempt at competing with Nvidia in the GPU race with a high-performance x86-based discrete graphics processor.
“We are excited to be an early evaluator of the Intel MIC Architecture since it promises to provide performance and power efficiency similar to GPU-based solutions on highly parallel workloads, but most importantly without the need for new programming models,” says David Hudak, OSC program director for cyber infrastructure and software development.
Intel’s mission statement is that the Intel MIC will target high-performance computing, workstation, and data center markets. They are boldly stating that this new design will eventually pave the way forward for exascale computing by 2018.
In a wise move, Intel has made the MIC architecture compatible with existing programming tools and methods, such as C, C++, and FORTRAN source code. Programs written for Intel’s MIC products can be compiled and run on standard Intel Xeon processors.